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IEEE 802.11 defines DSSS, for data rates of 1 Mbit/sec and 2 Mbit/sec.

IEEE 802.11b additionally defines HR/DSSS (High Rate Direct Sequence Spread Spectrum), for data rates of 5.5 Mbit/sec and 11 Mbit/sec.

- Uses 5 MHz wide channels in the 2.4 GHz ISM (Industrial Scientific
Medicine) band:
Channel 1 centred on 2412 MHz.

Channel 2 centred on 2417 MHz.

...

Channel 11 centred on 2462 MHz.

- Regardless of the data rate, transmits at 11 Msymbols/sec, giving a bandwidth of 22 MHz. Adjacent networks must use channels at least 5 numbers (i.e. 25 MHz) apart.

- Uses DPSK (Differential Phase Shift Keying). Each symbol uses one of
the phase shifts shown on this I/Q diagram:
This is
**differential**phase shift keying, so the phase of the carrier during a symbol is shifted by the specified angle with respect to the phase of the carrier during the**previous**symbol.

- DSSS: the data stream is
**chipped**using the11-chip **Barker sequence**:+1 −1 +1 +1 −1 +1 +1 +1 −1 −1 −1

- 1 Mbit/sec data rate: each data bit modifies one 11-chip sequence:
The modulation scheme uses DBPSK (Differential Binary Phase Shift Keying). Note how the transmitted data rate (and hence the bandwidth) is increased 11 fold, but the susceptibility to noise is reduced – since each data bit can be recovered using a correlator to determine which 11 chip sequence is most likely to have been received.

0 ⇒ multiply each chip by +1, i.e. phase shift by 0° ⇒ +1 −1 +1 +1 −1 +1 +1 +1 −1 −1 −1 1 ⇒ multiply each chip by −1, i.e. phase shift by 180° ⇒ −1 +1 −1 −1 +1 −1 −1 −1 +1 +1 +1

- 2 Mbit/sec data rate: each pair of data bits modifies one 11-chip sequence:
The modulation scheme uses DQPSK (Differential Quadrature Phase Shift Keying).

00 ⇒ multiply each chip by +1, i.e. phase shift by 0° ⇒ +1 −1 +1 +1 −1 +1 +1 +1 −1 −1 −1 01 ⇒ multiply each chip by +i, i.e. phase shift by 90° ⇒ +i −i +i +i −i +i +i +i −i −i −i 11 ⇒ multiply each chip by −1, i.e. phase shift by 180° ⇒ −1 +1 −1 −1 +1 −1 −1 −1 +1 +1 +1 10 ⇒ multiply each chip by −i, i.e. phase shift by 270° ⇒ −i +i −i −i +i −i −i −i +i +i +i

- HR/DSSS: the chip sequence is no longer constant: CCK (Complementary
Code Keying) is used to transmit additional data information. The data stream
is
**chipped**using the8-chip sequence:s2.s3.s4 s3.s4 s2.s4 −s4 s2.s3 s3 −s2 +1

- 5.5 Mbit/sec data rate: the data is split into sets of 4 bits (b0, b1, b2, b3).

The last 2 bits (b2, b3) select one of 4 predetermined8-chip sequences, calculated by setting:s2 = +i (b2=0)The first 2 bits (b0, b1) select a phase rotation applied to the selected sequence.or−i (b2=1)

s3 = 0

s4 = +1 (b3=0)or−1 (b3=1)

- 11 Mbit/sec data rate: the data is split into sets of 8 bits (b0, b1, b2, b3, b4, b5, b6, b7).

The last 6 bits (b2, b3, b4, b5, b6, b7) select one of 64 predetermined8-chip sequences, calculated by setting:s2 = +1 (b2, b3=00)The first 2 bits (b0, b1) select a phase rotation applied to the selected sequence.or+i (b2, b3=01)or−1 (b2, b3=10)or−i (b2, b3=11)

s3 = +1 (b4, b5=00)or+i (b4, b5=01)or−1 (b4, b5=10)or−i (b4, b5=11)

s4 = +1 (b6, b7=00)or+i (b6, b7=01)or−1 (b6, b7=10)or−i (b6, b7=11)