Processor registers

Programme sequencer registers

Programme counter:

Programme counter PC [218x] (14 bits)
[219x] (24 bits)

The PC register has its own stack. PC is pushed onto the stack by CALL instructions or interrupts, and popped off the stack by RTS or RTI instructions.

The maximum stack depth is [218x] 16 words (of 14 bits).
[219x] 33 words (of 24 bits).

Status and control registers:

Arithmetic Status   ASTAT   (8 bits)  
b7  SS  = shifter input sign
b6  MV  = MAC overflow
b5  AQ  = ALU quotient
b4  AS  = ALU X input sign
b3  AC  = ALU carry
b2  AV  = ALU overflow
b1  AN  = ALU result negative
b0  AZ  = ALU result zero
Stack Status (read only)   SSTAT   (8 bits)  
b7   loop stack overflow
b6   loop stack empty
b5   status stack overflow
b4   status stack empty
b3   count stack overflow
b2   count stack empty
b1   PC stack overflow
b0   PC stack empty
Mode Status   MSTAT   (7 bits)  
b6   [218x] go mode enable (disable causes halt during bus grant)
[219x] select primary/secondary DAG register bank
b5   timer enable (disable stops timer decrementing)
b4   MAC result placement mode
b3   AR saturation mode enable (i.e. an overflow saturates rather than wrapping around)
b2   ALU overflow latch mode enable (i.e. AV status bit is "sticky")
b1   bit reverse mode enable
b0   select primary/secondary computational register bank
    ICNTL   (5 bits)    
    IMASK   (10 bits)    
    IFC   (16 bits)    

The status registers have their own stack. ASTAT, MSTAT and [218x only] IMASK are pushed onto the stack by interrupts, and popped off the stack by RTI instructions.

Computational registers

There are two sets of these registers, selected by the least significant bit of the MSTAT register. This bit can be set/cleared by the ENA/DIS SEC_REG instructions.

Arithmetic Logic Unit (ALU) registers:

X input register file   AX0   (16 bits)
    AX1   (16 bits)
Y input register file   AY0   (16 bits)
    AY1   (16 bits)
Result register   AR   (16 bits)
Feedback register   AF   (16 bits)

Multiplier Accumulator (MAC) registers:

X input register file   MX0   (16 bits)        
    MX1   (16 bits)        
Y input register file   MY0   (16 bits)        
    MY1   (16 bits)        
Result register   MR   (40 bits)   MSB   MR2 (8 bits)
                MR1 (16 bits)
            LSB   MR0 (16 bits)
Feedback register   MF   (16 bits)        

Barrel Shifter registers:

Shifter Input   SI   (16 bits)        
Shifter Exponent   SE   (8 bits)        
Shifter Block exponent   SB   (5 bits)        
Shifter Result   SR   (32 bits)   MSB   SR1 (16 bits)
            LSB   SR0 (16 bits)

Data Address Generator (DAG) registers

    DAG1   DAG2    
Index register file   I0...I3   I4...I7   (unsigned 14 bits)
Modify register file   M0...M3   M4...M7   (signed 14 bits)
Length register file   L0...L3   L4...L7   (unsigned 14 bits)

dm(In,Mm) means:

1.  Read/write the address specified in In.
2.  If Ln = 0, use linear addressing: set In := In + Mm.
  If Ln > 0, use modulo (circular) addressing: set (In - base) := ((In - base) + Mm) mod Ln
where base is the base address of the buffer, and Ln contains the length of the buffer..

Note: In and Mm must be in the same DAG (either DAG1 or DAG2).

Miscellaneous registers

PX   (8 bits)   Provides the least significant 8-bits when transferring between a 16-bit data memory location and a 24-bit programme memory location.